Due to the convergence of consumer electronics and internet-based services, many functions tend to be combined into a single device.
This convergence involves all fields of computing and communications, wires and networks, middleware, applications, services, and the like.
Besides, as concerns silicon technology, a major effort is made in order to reduce the chip count, integrating more and more functions into a single chip.
Multiprocessing systems have thus been proposed to achieve the delicate balance between programmable cores, special-purpose engines and dedicated logic to address complexity, performance capacity, power consumption, area and future scalability.
In addition, researchers have proposed the so-called System on-Chip concept (SoC) to overcome the limitations relating to the huge efforts necessary to adequately design computing system architectures.
Interconnections between programmable engines or microprocessors play a critical role in the deployment of multiprocessing architectures.
As concerns the System on-Chip, the Network on-Chip, which provides communication between the programmable engines, constitutes one of the main aspects to be considered for the operation and for the flexibility of the entire SoC. In particular, interconnection interfaces are of great importance and must be designed carefully as they constitute a critical link in the communication chain and must operate efficiently, with low latency while allowing full flexibility to the wild range of protocols that software will require to be run on top of them.
These efficient and flexible hardware primitives must be in addition few and simple to implement, so as to reduce costs and increase speed of operation.
In addition, they must be flexible enough so that multiple communication mechanisms and protocols can be implemented on top of them.
Although researchers have already proposed remote DMA and remote queues solutions for high performance computing systems, no cost effective solution has been proposed in the field of an embedded System on-Chip.
In view of the foregoing, a need exists for providing a multiprocessor architecture permitting the provision to a user of a simple and efficient way to program cores without taking into consideration the data transfer aspect between said cores.